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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver High-Performance Silicon-Gate CMOS
The MC54/74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has noninverting outputs and two active-low output enables. The HC244A is similar in function to the HC240A and HC241A. * * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 136 FETs or 34 Equivalent Gates
MC54/74HC244A
J SUFFIX CERAMIC PACKAGE CASE 732-03
1
20
20 1 20 1
N SUFFIX PLASTIC PACKAGE CASE 738-03 DW SUFFIX SOIC PACKAGE CASE 751D-04 SD SUFFIX SSOP PACKAGE CASE 940C-03 DT SUFFIX TSSOP PACKAGE CASE 948E-02
20 1 20 1
LOGIC DIAGRAM
2 4 6 8 11 13 15 17
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18 16 14 12 9 7 5 3 YA1 YA2 YA3 YA4 YB1 YB2 YB3 YB4 NONINVERTING OUTPUTS ENABLE A A1 YB4 A2 YB3 A3 YB2 A4 YB1
ORDERING INFORMATION Ceramic MC54HCXXXAJ Plastic MC74HCXXXAN SOIC MC74HCXXXADW SSOP MC74HCXXXASD TSSOP MC74HCXXXADT
A1 A2 A3 A4 DATA INPUTS B1 B2 B3 B4
PIN ASSIGNMENT
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC ENABLE B YA1 B4 YA2 B3 YA3 B2 YA4 B1
GND
FUNCTION TABLE
OUTPUT ENABLES 1 ENABLE A 19 ENABLE B PIN 20 = VCC PIN 10 = GND Inputs Enable A, Enable B L L H A, B L H X Outputs YA, YB L H Z
Z = high impedance
2/97
(c) Motorola, Inc. 1997
1
REV 7
DataSheet 4 U .com
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MC54/74HC244A
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IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I I I II I I II I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIII IIIIIIIIIIII I I II I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I III I I I I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I II I I I I I I II I II II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIII II I III I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I II IIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I
III I I I I I IIIIIIIIIIIIIIIIIIIII I II II IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I III I I I I I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 35 75 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package SSOP or TSSOP Package Storage Temperature mW Tstg TL - 65 to + 150 260 300
_C _C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, SSOP or TSSOP Package) (Ceramic DIP)
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_ C from 65_ to 125_ C Ceramic DIP: - 10 mW/_ C from 100_ to 125_ C SOIC Package: - 7 mW/_ C from 65_ to 125_ C SSOP or TSSOP Package: - 6.1 mW/_ C from 65_ to 125_ C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter
Min 2.0 0
Max 6.0
Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
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VCC - 55 0 0 0 + 125 1000 500 400
_C
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_ C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
v 85_ C v 125_ C
1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2
Unit V
Minimum High-Level Input Voltage
Vout = VCC - 0.1 V |Iout| 20 A
v v v
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V |Iout| 20 A
V
VOH
Minimum High-Level Output Voltage
Vin = VIH |Iout| 20 A Vin = VIH
V
|Iout| |Iout| |Iout|
v 2.4 mA v 6.0 mA v 7.8 mA
2.48 3.98 5.48
2.34 3.84 5.34
MOTOROLA
2
High-Speed CMOS Logic Data DL129 -- Rev 6
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MC54/74HC244A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
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IIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I III I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIII II I I III I I I I I I II I III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIII I I II I I I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIII IIIIIIIIIIII I I II I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I
Guaranteed Limit Symbol VOL Parameter Test Conditions VCC V 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 - 55 to 25_ C 0.1 0.1 0.1
v 85_ C v 125_ C
0.1 0.1 0.1 0.1 0.1 0.1 0.4 0.4 0.4
Unit V
Maximum Low-Level Output Voltage
Vin = VIL |Iout| 20 A
v
Vin = VIL
Iin IOZ
Maximum Input Leakage Current Maximum Three-State Leakage Current Maximum Quiescent Supply Current (per Package)
|Iout| |Iout| |Iout| Vin = VCC or GND
v 2.4 mA v 6.0 mA v 7.8 mA
0.26 0.26 0.26
0.33 0.33 0.33
0.1 0.5
1.0 5.0
1.0 10
A A
ICC
Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 A
6.0
4.0
40
160
A
NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol S bl tPLH, tPHL
Parameter P
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- --
- 55 to 25_ C 96 50 18 15
v 85_ C
115 60 23 20
v 125_ C
135 70 27 23 165 80 33 28 165 80 33 28 90 32 18 15 10 15
Unit Ui ns
Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3)
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4)
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110 60 22 19 110 60 22 19 60 23 12 10 10 15
140 70 28 24 140 70 28 24 75 27 15 13 10 15
ns
tPZL, tPZH
Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4)
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 3)
ns
Cin
Maximum Input Capacitance
pF pF
Cout
Maximum Three-State Output Capacitance (Output in High-Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 34
CPD
P i Power Di i i C Dissipation Capacitance (P B ff )* (Per Buffer)*
F pF
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6
3
MOTOROLA
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MC54/74HC244A
SWITCHING WAVEFORMS
tr DATA INPUT A OR B tPLH OUTPUT YA OR YB tTLH 90% 50% 10% tTHL 90% 50% 10% tPHL OUTPUT Y tf VCC GND ENABLE A OR B 50% GND tPZL 50% tPZH OUTPUT Y 50% tPHZ 10% 90% tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE VCC
Figure 1.
Figure 2.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
CL*
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 3. Test Circuit
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PIN DESCRIPTIONS
Figure 4. Test Circuit
INPUTS A1, A2, A3, A4, B1, B2, B3, B4 (Pins 2, 4, 6, 8, 11, 13, 15, 17) Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs, when the outputs are enabled. CONTROLS Enable A, Enable B (Pins 1, 19) Output enables (active-low). When a low level is applied
to these pins, the outputs are enabled and the devices function as noninverting buffers. When a high level is applied, the outputs assume the high impedance state. OUTPUTS YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4 (Pins 18, 16, 14, 12, 9, 7, 5, 3) Device outputs. Depending upon the state of the output- enable pins, these outputs are either noninverting outputs or high-impedance outputs.
MOTOROLA
4
DataSheet 4 U .com
High-Speed CMOS Logic Data DL129 -- Rev 6
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MC54/74HC244A
LOGIC DETAIL
TO THREE OTHER A OR B INVERTERS
ONE OF 8 INVERTERS VCC
DATA INPUT A OR B
YA OR YB
ENABLE A OR ENABLE B
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High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
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MC54/74HC244A
OUTLINE DIMENSIONS
J SUFFIX CERAMIC PACKAGE CASE 732-03 ISSUE E
B A F C L
DIM A B C D F G H J K L M N NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15_ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0 15 _ _ 0.010 0.040
20 1
11 10
N H D
SEATING PLANE
G
K
J M
-A-
20 11
N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E
B
1
10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
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K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
-A-
20 11
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E
10X
-B-
1 10
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
MOTOROLA
6
4U D a t a S h e e t. c o m
High-Speed CMOS Logic Data DL129 -- Rev 6
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MC54/74HC244A
OUTLINE DIMENSIONS
SD SUFFIX PLASTIC SSOP PACKAGE CASE 940C-03 ISSUE B
20X
K REF 0.12 (0.005)
M
TU
S
V
0.25 (0.010)
S
N M N
L/2 L
PIN 1 IDENT
20
11
B
1 10
F DETAIL E K J
0.20 (0.008)
M
TU
S
SECTION N-N -W-
0.076 (0.003) -T-
SEATING PLANE
C D G H
DETAIL E
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20X
K REF
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
TU
S
0.15 (0.006) T U
S
0.10 (0.004)
M
V
S
2X
L/2
20
11
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
DataSheet 4 U .com
High-Speed CMOS Logic Data DL129 -- Rev 6
7
IIII IIII IIII
EEE CCC EEE CCC
K1 K K1 DETAIL E
A -V-
-U-
J1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.07 7.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.59 0.75 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.278 0.288 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.023 0.030 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8 _
SECTION N-N
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 _ _
M
DIM A B C D F G H J J1 K K1 L M
-W-
MOTOROLA
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MC54/74HC244A
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DataSheet 4 U .com
MC74HC244A/D High-Speed CMOS Logic Data DL129 -- Rev 6
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